System for switching high-capacity and variable length packets

ABSTRACT

In a system for switching high-capacity and variable length packets from m input ports to n output ports, k Banyan networks are connected into a ring by means of at least n parallel lines, said input ports are connected to inputs of said Banyan networks in a dispersed manner by means of m input modules, misroute tag check parts are connected to outputs of said Banyan networks as well as to inputs of n output modules whose outputs are connected to said output ports. Each of plural unit switches constituting a Banyan network is constructed such that when an input packet cannot be sent to a desired output, the relevant packet is outputted to a non-occupied output of the relevant Banyan network. When the misroute tag check part finds that the misroute tag is set, the relevant packet is sent to a next stage Banyan network, but when the misroute check tag is not set, the relevant packet is outputted to an output module connected to a desired output. The input module stores a packet from the input port and a packet from a misroute tag check part and sends one of these packets selectively to a succeeding Banyan network.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a system for switching high-capacity andvariable length packets from plural input ports to plural output ports.

2. Related Art Statement

A common bus system is currently used in most major IP(internetprotocol) routers and has been used in almost all commercially availableIP routers. FIG. 1 shows diagrammatically a packet switch of the commonbus system. Each of plural input ports gets or acquires a right of usinga common bus according to the round robin method and sends or broadcastsa packet on to the common bus. Each of plural outputs ports receives abroadcast packet addressed to the relevant output port. Therefore, inorder to make a packet loss within the router to be zero, an operationspeed of the common bus should be not lower than a value represented by(a transmission speed of each ports)×(the number of the ports).

The common bus system has advantages that variable-length packets can beexchanged and the number of circuit elements constituting the router canbe reduced, but the transmission speed of the common bus must beincreased in proportion to an increase in the number of the input andoutput ports. Therefore, due to physical limits of circuit elements, itis very difficult to realize a mass switching system having a bit ratemore than one Tbps (terabit per second) by means of the common bussystem.

FIG. 2 shows a Banyan network by means of which a mass switch can berealized by connecting unit switches in a multiple-stage mode. In theBanyan network, transmission paths exist between each of the input portsand all the output ports.

The Banyan network is suitable to realize the high-speed andhigh-capacity packet switching system, because all the unit switcheswithin the Banyan network operate in parallel. However, as shown in FIG.3, it has a drawback that when plural packets are inputted into the sameinput port, undesired internal blocking occurs. In FIGS. 2 and 3, theunit switch is formed by a 2×2 unit switch, but 4×4 unit switch, 8×8unit switch, 16×16 unit switch and so on may be used to realize similarpacket switching systems.

In order to reduce the internal blocking in the Banyan network, therehas been proposed a tandem Banyan network. In this tandem Banyannetwork, plural Banyan networks are arranged in tandem as shown in FIG.4. In the tandem Banyan network, all the packets are inputted to a firststage Banyan network among the Banyan networks (in FIG. 4, the mostleft-hand side Banyan network), and when the internal blocking occurs inthis first stage Banyan network, a misroute tag is set on the relevantpacket and the packet is outputted to an empty output port which is notoccupied by other packet. In this manner, after the packet has passedthrough the first stage Banyan network, the packet is inputted to asecond stage Banyan network of the tandem Banyan network. On the otherhand, a packet which has succeeded to be outputted to a desired ordenoted output port of the first stage Banyan network is sent to anoutput buffer without passing through the remaining Banyan networks.

As explained above, in the tandem Banyan network, upon the occurrence ofan internal blocking, a packet can be inputted to a succeeding one ormore Banyan networks until the relevant packet arrives at a desired ordestined output ports, and therefore almost all internal blockings canbe avoided. In other words, in the tandem Banyan network, an internalblocking could not be avoided only when misroute tags are set at all theBanyan networks from the first stage to the last stage.

The tandem Banyan network is a valuable means for reducing the internalblocking in the Banyan network. However, in the tandem Banyan network,all packets are first inputted to the first stage Banyan network, andwhen an internal blocking might occur in the first stage Banyan network,the relevant packet is inputted to the second stage Banyan network andso on. Therefore, when an input traffic is large, a rate of occurrenceof internal blocking in the first stage Banyan network becomes high andthis results in an increase of a rate at which packets are inputting toBanyan networks after the second stage. This might cause an increase ina switching delay as well as an increase in a fluctuation of theswitching delay. Furthermore, there might arise a problem that a rate ofoccurrence of a wrong order of packets is increased in accordance withthe increase in a fluctuation of switching delay.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a novel and useful systemfor switching high-capacity and variable length packets, in which theabove mentioned problems in the known tandem Banyan network can bemitigated and a rate of occurrence of internal blocking can be reducedand the switching delay and the delay fluctuation can be decreased.

According to the present invention, a system for switching high-capacityand variable length packets comprises:

m (plural) input ports;

n (plural) output ports;

k (plural) Banyan networks connected into a ring by means of at least nparallel lines, each Banyan network having at least n inputs and atleast n outputs;

m input modules each of which is connected to a respective one of said minput ports, said input modules being further connected to said inputsof said k Banyan networks;

m sets of misroute tag check parts, each set including at least nmisroute tag check parts, respective misroute tag check parts in eachset being connected to respective outputs of each Banyan networks; and

n output modules each having an output connected to a respective one ofsaid output ports and inputs each connected to one of misroute tag checkparts of each set;

wherein each of plural unit switches constituting a Banyan network isconstructed such that when an input packet cannot be sent to a desiredoutput, the relevant packet is outputted to a non-occupied output of therelevant Banyan network,

said misroute tag check part checks whether a misroute tag of aninputted packet is set or not, and when the misroute tag is set, therelevant packet is sent to a next stage Banyan network, but when themisroute check tag is not set, the relevant packet is outputted to anoutput module connected to a desired output; and

said input module is constructed to store a packet from the input portand a packet from a misroute tag check part and to send one of thesepackets selectively to a Banyan network of a next stage.

In the packet switching system according to the invention, as shown inFIG. 5, plural Banyan networks are connected in the form of a ring andplural input ports are connected to these Banyan networks in a dispersedmanner. Thus, an input traffic is dispersed and an apparent inputtraffic of each Banyan networks can be reduced. For example, providedthe number of the Banyan networks is N, in the known tandem Banyannetwork, a total amount of traffic is inputted into the Banyan networkof the first stage, but in the packet switching system according to theinvention, it is sufficient that each Banyan network receive 1/N of thetotal traffic amount. In this manner, the input traffic is dispersedamong a plurality of Banyan networks connected into a ring. Due to thisdispersing effect, an apparent input traffic to each of the Banyannetworks is reduced, and thus a rate of occurrence of the internalblocking in Banyan networks is decreased as compared with the tandemBanyan network and a packet switching delay and a fluctuation of thepacket switching delay can be decreased.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a known packet switch of the commonbus system;

FIG. 2 is a block diagram illustrating the Banyan network;

FIG. 3 is a schematic view representing an occurrence of internalblocking in the Banyan network;

FIG. 4 is a block diagram depicting the known tandem Banyan network;

FIG. 5 is a block diagram showing a basic structure of the packetswitching system according to the invention;

FIG. 6 is a block diagram illustrating an embodiment of the packetswitching system according to the invention;

FIG. 7 is a block diagram showing a detailed construction of a misroutetag check part of the packet switching system shown in FIG. 6;

FIG. 8 is a block diagram depicting a detailed construction of an inputmodule of the packet switching system shown in FIG. 6;

FIG. 9 is a block diagram showing a detailed construction of an outputmodule of the packet switching system shown in FIG. 6;

FIG. 10 is a block diagram illustrating a structure of 64×64 Banyannetwork constructed by 4×4 unit switches;

FIG. 11 is a graph showing a relationship between the number of Banyannetwork plains and a packet loss rate; and

FIG. 12 is a graph representing percentages at which input packets canbe outputted at respective Banyan networks.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

FIG. 6 is a block diagram showing an embodiment of the packet switchingsystem according to the invention. The packet switching system comprisesm input ports I_(h) (h=1, 2, . . . , m) and m input modules IM_(h) (h=1,2, . . . , m), said input ports I_(h) are connected to said inputmodules IM_(h). In the present embodiment, first two input ports I₁ andI₂ are connected to a first input module IM₁, and a second input moduleIM₂, respectively, the second two input ports I₃ and I₄ are connected toa third input module IM₃ and a fourth input module IM₂, respectively,and so on. The packet switching system further comprises k Banyanneworks B_(i) (i=1, 2, . . . , k) each of which includes n outputs, nximisroute tag check parts MT_(h,i) and n output modules OM_(j) (j=1, 2, .. . , n) each connected to respective output ports O_(j). In theembodiment shown in FIG. 6, it is assumed that m=n=8 and k=4, but thesenumbers may be set to any desired values.

The Banyan network B_(i) can achieve the high-capacity switching byarranging a number of unit switches in a multiple-stage connection asshown in FIG. 2. When a packet cannot be sent to an output of a Banyannetwork leading to a desired output port O_(j), each unit switch sets amisroute tag of the relevant packet and sends this packet to an emptyoutput. In FIG. 2, although the Banyan network is composed of 2×2 unitswitches, similar multiple-stage connections may be realized by using4×4, 8×8, 16×16 or 32×32 unit switches. The numbers of the inputs andoutputs of each of the Banyan networks must be at least the number n ofthe output ports. The Banyan networks are connected in the form of ringby means of at least n lines. In this embodiment, it is assumed that thepackets run in a counterclockwise direction along the Banyan networksconnected in the form of ring.

The misroute tag check part MT_(h,i) has a 1×2 switching function. Themisroute tag check part checks whether the misroute tag of an inputpacket is set or not, and when the misroute tag is set, the relevantpacket is switched to a succeeding Banyan network B_(i) and when themisroute tag is not set, the packet is sent to an output module O_(mj).

As shown in FIG. 8, the input module IM_(h) comprises first and secondFIFO (First In First Out) buffers 11, 12 and a selector 13. The firstand second FIFO buffers 11 and 12 store packets sent from an input portI_(h) and a misroute tag check part MT_(h,i), respectively. The selector13 selects a packet from either one of the first and second FIFO buffers11 and 12, and sends the thus selected packet into a Banyan network of asucceeding stage. In this embodiment, it is assumed that a packet from amisroute tag check part MT_(h,i) has a higher priority than a packetfrom an input port I_(h). Therefore, when a packet from a misroute tagcheck part MT_(h,i) is stored in the first FIFO buffer 11, the selector13 sends this packet into a succeeding Banyan network.

Moreover, when both traffic from an input port I_(h) and a misroute tagcheck part MT_(h,i) are 100 percent, the first and second FIFO buffers11 and 12 might overflow. Therefore, all elements in the Banyan networkring including the input module IM_(h) and other should be operated at ahigher transmission rate than that of the input port I_(h) by two.

As shown in FIG. 9, the output module OM_(j) comprises plural timingcontrol buffers 21, a common bus 22 connected to said timing controlbuffers, a control part 23 and an output buffer 24. The timing controlbuffers 21 store packets outputted from respective Banyan networksB_(i). The control part 23 controls the common bus 22 to give a priorityof using the common bus 22 to each of the timing control buffers 21according to the round robin method. When a timing control buffer 21gets a priority of using the common bus 22, a packet stored in therelevant timing control buffer 21 is sent to the output buffer 24 viathe common bus.

Next a process of switching a packet inputted from an input port I_(h)to a desired output port O_(j) will be explained.

First, a packet is inputted to an input port I_(h) and is stored in asecond FIFO buffer 12 provided in an input module IM_(h) connected tothe relevant input module. As stated above, in the input module IM_(h),a higher priority is given to a packet from the misroute tag check partMT_(h,i) than to a packet from the input port I_(h), and therefore thepacket from the input port is inputted to the Banyan network B_(i) viathe selector 13 only when a packet from the misroute tag check partMT_(h,i) is not stored in the first FIFO buffer 11.

The packet inputted to the Banyan network B_(i) is switched among theunit switches provided therein. In this case, if an output connected toa desired output port O_(j) to which the relevant packet is to bedestined is occupied, the misroute tag in the packet header is set andthe packet is outputted to a non-occupied output, The packet passedthrough the Banyan network B_(i) is then sent to a misroute tag checkpart MT_(h,i) connected to this non-occupied output.

In the misroute tag check part MT_(h,i), it is checked whether themisroute tag of the inputted packet is set or not, and when the misroutetag is set, the relevant packet is sent to a next stage Banyan network.When the misroute tag of the inputted packet is not set, the packet issent to an output module OM_(j).

The packet entered into the output module OM_(j) is stored in the timingcontrol buffer 21 until a priority of usage of the common bus 22 isgiven. Upon getting the priority, the packet is inputted into the outputbuffer 24 via the common bus 22 and then is outputted from the packetswitching system via an output port O_(j).

A performance of the known tandem Banyan network and that of the packetswitching system according to the invention have been simulated. In thissimulation, it is assumed that the Banyan network is formed by a 64×64Banyan network using 4×4 unit switches as shown in FIG. 10, atransmission speed of the port is 155.52 Mbps, the input load is 90percent and the IP datagram is variable length in the range between 21and 1500 octets.

FIG. 11 shows a relationship between the number of the Banyan networksand a packet loss rate. As can be seen from FIG. 11, when the number ofstages of Banyan networks increases, the packet loss rate decreases inboth the known tandem Banyan network and the packet switching systemaccording to the invention, but, in the packet switching systemaccording to the invention, since the input traffic is dispersed, thepacket loss rate is lower than that in the tandem Banyan network.Furthermore, the packet loss rate in the packet switching systemaccording to the invention converges faster than the tandem Banyannetwork, and therefore the high performance can be attained with thesmaller number of Banyan network stages. This is a great advantage froma viewpoint of design.

FIG. 12 shows a percentage of input packets which can be sent to outputports over what number of Banyan networks in the known tandem Banyannetwork and the packet switching system according to the invention bothhaving six Banyan network stages.

FIG. 12 shows a number of Banyan networks stages through which the inputpackets travel in the known tandem Banyan network and in the packetswitching system according to the invention, both having six Banyannetwork stages.

What is claimed is:
 1. A system for switching high-capacity and variablelength packets comprising: m input ports; n output ports; k Banyannetworks connected into a ring by means of at least n parallel lines,each Banyan network having at least n inputs and at least n outputs,each of m, n, and k being integers; m input modules each of which isconnected to a respective one of said m input ports, said input modulesbeing further connected to said inputs of said k Banyan networks; m setsof misroute tag check parts, each set including at least n misroute tagcheck parts, respective misroute tag check parts in each set beingconnected to respective outputs of each Banyan network; and n outputmodules each having an output connected to a respective one of saidoutput ports and inputs each connected to one of misroute tag checkparts of each sets; wherein each of plural unit switches constituting aBanyan network is constructed such that when an input packet cannot besent to a desired output, the relevant packet is outputted to anon-occupied output of the relevant Banyan network; said misroute tagcheck part checks whether a misroute tag of an inputted packet is set ornot, and when the misroute tag is set, the relevant packet is sent to anext stage Banyan network, but when the misroute check tag is not set,the relevant packet is outputted to an output module connected to adesired output; and said input module is constructed to store a packetfrom the input port and a packet from a misroute tag check part and tosend one of these packets selectively to a Banyan network of a nextstage.
 2. A packet switching system according to claim 1, wherein eachof said input modules comprises a first FIFO buffer storing a packetfrom a misroute tag check part, a second FIFO buffer storing a packetfrom an input port, and a selector selecting one of packets stored insaid first and second FIFO buffers and sending a selected packet to asucceeding Banyan network.
 3. A packet switching system according toclaim 2, wherein a packet from a misroute tag check part has a higherpriority than a packet from an input port, and when a packet from amisroute tag check part is stored in the first FIFO buffer, the selectorsends this packet to the succeeding Banyan network.
 4. A packetswitching system according to claim 1, wherein each of said outputmodule comprises timing control buffers storing packets from the Banyannetworks, a common bus connected to said timing control buffers, acontrol part connected to said common bus to give a priority to each ofthe timing control buffers according to the round robin method, and anoutput buffer sending a packet on the common bus to an output port.
 5. Apacket switching system according to claim 1, wherein all elements inthe input ports, Banyan networks, misroute tag check parts and outputmodules are operated at a higher transmission rate than that of atransmission rate of the input ports by two.